1. Field of the Invention
The present invention relates to microelectronic contacts for use with semiconductor devices and the like.
2. Description of Related Art
The demand for ever-smaller and more sophisticated electronic components has driven a need for smaller and more complex integrated circuits (ICs). The ever-smaller ICs and high lead counts, in turn, require more sophisticated electrical connection schemes, both in packaging for permanent or semi-permanent attachment, and for readily demountable applications such as testing and burn-in.
For example, many modern IC packages have smaller footprints, higher lead counts and better electrical and thermal performance than IC packages commonly used only a few years ago. One such compact IC package is the ball grid array (BGA) package. A BGA package is typically a rectangular package with terminals, normally in the form of an array of solder balls, protruding from the bottom of the package. These terminals are designed to be mounted onto a plurality of bonding pads located on the surface of a printed circuit board (PCB) or other suitable substrate. The solder balls of the array are caused to reflow and bond with bonding pads (terminals) on a mating component, such as by passing the component with the mounted BGA package through an ultrasound chamber or like thermal energy source, and then removing the energy source to cool and harden the solder and form a relatively permanent bond. Once melted and re-hardened, the solder ball connections cannot readily be re-used, if at all. Hence, separate, readily demountable contact elements are required to contact the terminal pads of the IC or the solder balls of the BGA package during testing and burn-in.
The advantages of readily demountable contact elements for use in compact packaging and connection schemes have previously been recognized. Readily demountable, flexible and resilient microelectronic spring contacts for mounting directly to substrates such as ICs are described in U.S. Pat. No. 5,917,707 to Khandros et al. Among other things, the '707 patent discloses microelectronic spring contacts that are made using a wire bonding process that involves bonding a very fine wire to a substrate, and subsequent electro-plating of the wire to form a resilient element. These microelectronic contacts have provided substantial advantages in applications such as back-end wafer processing, and particularly for use as contact structures for probe cards, where they have replaced fine tungsten wires. These same or similar contact elements may also be used to make electrical connections between semiconductor devices in general, for making both temporary (readily demountable) and more permanent electrical connections in almost every type of electronic device.
Presently, however, the cost of fabricating fine-pitch spring contacts has limited their range of applicability to less cost-sensitive applications. Much of the fabrication cost is associated with manufacturing equipment and process time. Contacts as described in the aforementioned patents are fabricated in a serial process (i.e., one at a time) that cannot be readily converted into a parallel, many-at-a-time process. Thus, new types of contact structures, referred to herein as lithographic type microelectronic spring contacts, have been developed, using lithographic manufacturing processes that are well suited for producing multiple spring structures in parallel, thereby greatly reducing the cost associated with each contact.
Exemplary lithographic type spring contacts, and processes for making them, are described in the commonly owned, co-pending U.S. patent application Ser. No. 09/032,473 filed Feb. 26, 1998, by Pedersen and Khandros, entitled “LITHOGRAPHICALLY DEFINED MICROELECTRONIC CONTACT STRUCTURES,” and Ser. No. 60/073,679, filed Feb. 4, 1998, by Pedersen and Khandros, entitled “MICROELECTRONIC CONTACT STRUCTURES.” These applications disclose methods for fabricating the spring structures using a series of lithographic steps, thereby building up the height of the spring contact with several layers of plated metal that may be patterned using various lithographic techniques. Microelectronic spring contacts are preferably provided with ample height to compensate for any unevenness in the mounting substrate and to provide space for mounting components, such as capacitors, under the spring contact.
Methods of achieving adequate height in a single lithographic step, i.e., a single resilient layer, and exemplary structures made thereby, are disclosed in the commonly owned, co-pending U.S. patent application Ser. No. 09/364,788, filed Jul. 30, 1999 by Eldridge and Mathieu, entitled “INTERCONNECT ASSEMBLIES AND METHODS,” and Ser. No. 09/710,539, filed Nov. 9, 2000, by Eldridge and Wenzel, entitled “LITHOGRAPHIC SCALE MICROELECTRONIC SPRING STRUCTURES WITH IMPROVED CONTOURS.” The foregoing applications disclose spring elements made from a single layer of metal. The metal layer is plated over a patterned three-dimensional layer of sacrificial material, which has been shaped using a micromachining or molding process. The sacrificial layer is then removed, leaving a free-standing spring contact having the contoured shape of the removed layer.
A need therefore exists for an improved microelectronic spring contact, and method of making it, that achieves or improves upon the performance of multi-layer and single-layer spring contacts at a substantially lower cost. The spring contact should be useful in very dense fine-pitch arrays for directly connecting to IC's and like devices, and be capable of making both relatively demountable and relatively permanent (e.g., soldered) connections.
Moreover, it is desirable that the microelectronic spring contact be useful in compact packaging schemes, where low cost, demountability, and resiliency are important. Exemplary applications may include portable electronic components (cellular phones, palm computers, pagers, disk drives, etc.), that require packages smaller than BGA packages. For such applications, solder bumps are sometimes deposited directly onto the surface of an IC itself and used for attachment to the printed circuit board (PCB). This approach is commonly referred to as direct chip attach or flip-chip. The flip-chip approach is subject to various disadvantages. One key disadvantage is the requirement for a polymer underfill beneath a die. The underfill is required to reduce thermal stresses caused by the relatively low thermal expansion of the silicon die relative to the typically much higher expansion of resin-based PCB's. The presence of the underfill often makes it infeasible to rework the component. Consequently, if the IC or its connection to the PCB is defective, the entire PCB usually must be discarded.
Another type of BGA package, the chip-scale ball grid array or a chip scale package (CSP), has been developed to overcome this disadvantage of flip-chips. In a chip scale package, solder ball terminals are typically disposed underneath a semiconductor die in order to reduce-package size, and additional packaging elements are present to eliminate the need for underfill. For example, in some CSP's, a soft compliant elastomer layer (or elastomer pad) is disposed between the die and the solder ball terminals. The solder ball terminals may be mounted onto a thin 2-layer flex circuit, or mounted to terminals on the compliant member. The IC is typically connected to terminals on the flex circuit or elastic member using a wire or tab lead, and the entire assembly (except the ball grid array) is encapsulated in a suitable resin.
The elastomeric member is typically a polymer, such as silicone, about 125 μm to 175 μm (5–7 mils) thick. The elastomer pad or layer essentially performs the function of and replaces the underfill used in flip-chips, that is, minimizes thermal mismatch stress between the die and the PCB. In other CSP designs, the IC is adhered directly to the surface of a two-layer flex circuit, and connected to terminals on the chip side of the flex circuit using wire leads. Solder balls are mounted on an opposite surface of the flex circuit. This design lacks an elastomer layer for decoupling the die from the PCB and, therefore, may not eliminate the need for underfill.
Current chip-scale package designs have a number of shortcomings. The elastomeric materials tend to absorb moisture, and if excessive moisture is absorbed, rapid outgassing of this moisture at reflow temperatures may cause the formation of voids in the elastomer layer, or bursting of the package. For example, moisture may be released from polymer materials in the elastomer and become trapped within the die attachment adhesive. Voids may then be formed when this trapped moisture expands during board assembly heating operations, typically causing cracking and package failure. Formation of such voids may be particularly problematic during reflow attachment to a PCB.
Another difficulty with chip-scale package designs is the process for integrating the elastomer member, which is typically done by picking and placing elastomer pads onto individual sites, or by screen printing and subsequently curing a fluid polymer. In either case, it may be difficult to meet the tight tolerances and package flatness required for a CSP application. For example, in a typical CSP design, the package flatness (planarity) should be less than about 25 μm (1 mil) to ensure that all solder balls establish contact with PCB upon reflow. This level of flatness may be difficult to achieve using prior art processes for depositing the elastomeric materials.
Therefore, it is further desirable to provide an improved microelectronic contact element for applications such as CSPs and flip-chips.